How Does the E5’s Second Data Pointer Work?

The E5 is based on the standard 8051 microcontroller architecture. The original 8051 architecture has a single 16-bit address pointer for the 8051’s external data (XDATA) memory space. In 8051 assembly code, this address pointer is called DPTR. Because the 8051 is an 8-bit microcontroller, the 16-bit data pointer is controlled by two byte-wide registers, DPH (data pointer high-byte) and DPL (data pointer low-byte).

The Triscend E5 CSoC device has two 16-bit data pointers, as shown in Figure 1. The DPTR address originates from either the original 8051 data pointer, DPH and DPL, or from the second data pointer, called DPH1 and DPL1. The DPS register selects whether the DHL, DPL registers form the 16-bit DPTR address or whether the DPH1, DPL1 registers form the address.

Figure 1. Diagram showing the E5’s two data pointers.

The E5 is binary code compatible with the original 8051. All code references to DPTR use the currently selected data pointer.

Here is an example using 8051 assembly language. In this example,

MOV DPS,#0 ; select DPH,DPL as data pointer, DPTR

MOV A,@DPTR ; read value at DPTR address into accumulator

INC DPS ; select DPH1,DPL1 as data pointer, DPTR

MOV @DPTR, A ; write value in accumulator to DPTR address

The DPTR is commonly used to copy data from one are of XDATA memory to another. The following examples show how to copy 64 bytes of XDATA from one region of memory to another. The following examples assume that the source data starts at XDATA address 2000h and the data destination starts at XDATA address 3000h.

The two examples demonstrate coding differences between the original 8051 and using the two data pointers on the E5 device. Both examples also show the number of E5 instruction cycles required to copy the data.

Original 8051 Code

Using just the original 8051 architecture, the data copy routine would use the standard 8051 SFRs as shown below.

MOV R0,#20h ; source address high-byte

MOV R1,#00h ; source address low-byte

MOV R2,#30h ; destination address high-byte

MOV R3,#00h ; destination address low-byte

MOV R4,#64 ; number of bytes to copy

LOOP:

MOV DPH,R0 ; load source address high-byte, 2 cycles

MOV DPL,R1 ; load source address low-byte, 2 cycles

MOVX A,@DPTR ; read byte from source memory, 2 cycles

INC DPTR ; increment source memory pointer, 3 cycles

MOV R0,DPH ; save source address high-byte, 2 cycles

MOV R1,DPL ; save source address low-byte, 2 cycles

MOV DPH,R2 ; load destination address high-byte, 2 cycles

MOV DPL,R3 ; load destination address low-byte, 2 cycles

MOVX @DPTR,A ; write byte to destination memory, 2 cycles

INC DPTR ; increment destination pointer, 3 cycles

MOV R2,DPH ; save destination address high-byte, 2 cycles

MOV R3,DPL ; save destination address low-byte, 2 cycles

DJNZ R4,LOOP ; copy until R4=0, 3 cycles

Each byte copied requires 29 instruction cycles, or 1,856 total instruction cycles to copy all 64 bytes.

Using Second Data Pointer

MOV DPS,#01h ; select second data pointer

MOV DPTR,#3000h ; load destination address into current DPTR

DEC DPS ; select original data pointer

MOV DPTR,#2000h ; load the source address into current DPTR

MOV R4,#64 ; number of bytes to copy

LOOP:

MOVX A,@DPTR ; read byte from source memory, 2 cycles

INC DPTR ; increment source pointer, 3 cycles

INC DPS ; select DPH1,DPL1 as DPTR, 2 cycles

MOVX @DPTR,A ; write byte to destination, 2 cycles

INC DPTR ; increment destination pointer, 3 cycles

DEC DPS ; select DPH,DPL as DPTR, 2 cycles

DJNZ R4,LOOP ; copy until R4=0, 3 cycles

Using the second data pointer, each byte copied requires just 17 instruction cycles or 1,088 cycles total for all 64 bytes. Compared to the 1,856 cycles required by the original 8051 architecture, the E5’s second data pointer accomplishes the same task in 59% of the time. Furthermore, the dual data-pointer approach uses only one of the 8051’s general-purpose registers (R4) compared to the five registers required in the original approach (R0 through R4).

Do you want to move data really quickly? The E5 also has an embedded two-channel DMA controller that can move data every clock cycle, independent of the 8051 microcontroller.

See article #16746, “Using the E5 Embedded DMAController”.

E5 CSoC